摘要
实现了一款10比特200Msps采样速度的数模转换器。该数模转换器采用了8+2的分段结构,高8位比特使用温度码设计。文中详细分析了CMOS工艺下匹配问题,采取一定措施提高匹配性。该数模转换器采用3.3V供电电压,摆幅为2Vpp,提高了系统的抗干扰能力。在200Msps采样率下,后仿真结果可达到INL小于0.34LSB,DNL小于0.05LSB,有效比特数为9.9,SNDR达到61.7dB,SFDR为75.3dB。该DAC采用SMIC180nm CMOS工艺设计,整体面积为800*800μm2。
A 10 bits 200Msps current steering digital to analog converter was described in this work. The DAC consists of a unit current cell for 8MSBs, and a binary weighted array for 2LSBs. In this paper, mismatch problem is analysis in detail. This ADC was supplied at 3.3V, swing was 2Vpp, and the high swing improved the SNR. The integral nonlinearity error is less than 0.34LSB, and the differential nonlinearity error is less than 0.02LSB. The ENOB is 9.9, the SNDR is 61.7, the SFDR is 75.3dB. This work is designed under smicl80nm CMOS process. The total area is 800＊800 μ m2
出处
《中国集成电路》
2012年第5期44-47,91,共5页
China lntegrated Circuit
