位串行SVD处理器的设计

Design of Bit-serial Singular Value Decomposition Processor

奇异值分解(SVD)广泛应用于数字信号处理等领域.为提高SVD效率,Brent等提出一种由SVD处理器组成的阵列,应用并行JACOBI算法实现SVD.SVD处理器一般采用CORDIC位并行结构实现.本文比较CORDIC位并行结构和位串行结构,分析了位串行结构在硬件资源以及时钟频率上的优势,采用CORDIC位串行结构设计了SVD处理器,并结合位串行结构的特点对其进行了优化.仿真实验验证了该设计的正确性;CORDIC结构的对比实验表明,与位并行结构相比,位串行设计以一定的处理时间为代价,可以节约大量的硬件资源,适用于硬件资源紧缺的非实时场合.

The Singular Value Decomposition { SVD） is a critical computing process in many fields such as digital signal processing. To improve the computational efficiency of SVD, Brent proposed a systolic array consists of SVD processors for parallel computation of the SVD using JACOBI algorithm. Commonly, the bit-parallel CORDIC structure is used to design the SVD processor. In this pa- per, a bit-serial CORDIC design for SVD processor is proposed to reduce the consumption of hardware resource and increase the clock frequency. Simulation results show that, compared with bit-parallel CORDIC implementation, a bit-serial CORDIC implementation can save a lot of hardware resources at the cost of slowing the computation. It is very suitable for those non real-time applications with the lack of hardware resources.