VLSI互连线系统中的低介电常数材料与工艺研究

Low-k- Dielectric Materials and Related Technologies for VLSI Interconnect System

阐述了超大规模集成电路 ( VLSI)特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。具体总结了为提高 VLSI的速度而采用的低介电常数材料及其制备工艺 ,对在连线间形成空气间隙来降低线间电容的方法也进行了介绍。最后 ,展望了低介电常数材料在 VL SI互连线系统中的应用前景。

The issue of interconnect capacitance rising from very large scale integration(VLSI)with a decreased feature size and increased number of wiring layers is described.The low k dielectric materials required in order to improve the chip speed and related fabricating technologies are reviewed.A method of reducing capacitance by air gaps formed between metal lines during SiO 2 deposition is introduced.The application future of low k thin films in IC is also presented.