一种带有增益提高技术的高速CMOS运算放大器设计

Design of a high speed CMOS operational amplifier with gain boosting technique

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。

A fully differential opamp used in a high speed ADC was designed.The main amplifier is a folded cascode amplifier with SC CMFB.The opamp can be used in a 12 bit、100MS/s high speed Pipelined ADC with gain boosting and the triple-branch current reference technique.The operational amplifier is implemented in a standard 0.25 μm CMOS process,simulated with Spectre under Cadence.With 2.5 V power supply and 2 pF load capacitance has a DC gain of 124 dB,a unity gain bandwidth of 720 MHz,Slew Rate of 885 V/μs,4 ns settling time and 153dB CMRR.