CMOS集成电路的功耗优化和低功耗设计技术

Optimization and Design for Power Techniques for CMOS IC′s

总结了当前已发展出的各个层次的 CMOS低功耗设计技术和低功耗设计方法学的研究进展。重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术。

Various design for power techniques and design methodology,which can reduce power consumptions in CMOS digital IC′s while maintaining computational throughput,are examined and summarized.The optimization and asynchronous design of sequencing circuits and high level circuit design and optimizing techniques are described in particular.