软件无线电中频数字化模块的FPGA设计实现

Design and Implementation of FPGA of IF Digital Module in SDR

为了便于实施软件无线电系统中基带信号的处理,需对中频信号进行数字化下变频。论文构建了基于FPGA的数字下变频系统,该系统参照GSM系统标准,并与现有通信模式兼容。在该数字下变频系统中,数控振荡器采用坐标旋转矢量计算方法来实时计算所需的正、余弦样本值,以易于实现的流水线结构取代了传统的需占用的大量ROM资源的查找表。同时,通过多相结构的等效变换将抽取滤波模块以抽取滤波器来实现,并采用积分梳状(CIC)滤波器、CIC补偿滤波器、半带(HB)滤波器和FIR滤波器四级级联的结构。用Verilog语言实现了中频数字化系统模块的设计,Quartus II和MATLAB的仿真结果都验证了设计的正确性和系统处理的实时性。

In order to facilitate the implementation of processing baseband signal in software radio system, IF signal needed to be processed by digital down-conversion. Referencing the standard of GSM system, digital down-conversion system based on FPGA system, which is compatible with existing communication patterns, is structured in this paper. Numerically controlled oscillator, in digital down- conversion system, uses CORDIC （ Coordinate-rotation Digital Compute } to calculate the sine and cosine sample value real time, it replaces the traditional lookup tables structure, which need to consume large amounts of ROM resource, with pipeline organization which is easy to implement. Meanwhile,decimation filter is come true to achieve decimation filter module,by equivalent transformation of multi- phase structure, and its structure is cascading of the integrator comb （CIC ） filter, CIC ,half band （ HB ） filters and FIR filter. IF digitization system module is designed in Verilog language, and the results of Quartus II and MATLAB simulation verified the correctness of the design and the real-time of the system.