摘要
以太网技术的高速发展,使得利用以太网进行通信和数据交换已成为当今社会通信的潮流和方向。在很多以太网产品设计中都需要设计以太网接口电路,本文介绍了一种基于FPGA的10/100Mb/s以太网接口收发器的IP核设计。该IP核可工作于MII/RMII/SMII模式,通过FPGA验证可作为独立模块应用于相关以太网芯片设计中。
With the high speed development of Ethernet technology, very important for people to use telecommunications and information exchange. The interface circuit is necessary for Ethernet products, Ethernet for this article introduces a kind of IP design about 10/100Mb/s Ethernet receiver/transmitter based on FPGA. The IP core can work in MII/RMII/SMII mode, and can be applied in IC design of Ethernet independently.
出处
《中国集成电路》
2011年第8期23-29,共7页
China lntegrated Circuit
关键词
以太网
FPGA
CRC
IP
Ethemet
FPGA
CRC
Intellectual property fights
