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适合NAND闪存控制器的BCH纠错编译码器VLSI实现 被引量：2

VLSI Implementation of BCH Codec for NAND Flash Controller
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摘要 随着大容量MP3播放器、PMP播放器、数码相机、智能手机等消费电子产品的需求持续增长,MLC的NAND闪存已经取代SLC的NAND闪存成为市场主流。而存储容量的增大所带来良率与可靠性的下降,意味着我们需要纠错能力更强大的硬件编译码器来处理可能发生的错误。针对固态硬盘需要支持多通道的NAND闪存,纠错编译码器也要有能够处理并行I/O总线的能力,本文实现了可由软件配置、最大纠错能力t为可变的1~16b的BCH纠错编译码器,在计算错误位置多项式的过程中使用了修正的欧几里德算法。 Along with the increasing demand of mass storage in MP3 player, PMP player, Digital still camera, MLC NAND flash had replaced SLC NAND flash and become the main stream. The increasing storage capacity results in the decreasing of yield and reliability. It means that we need a powerful error correction hardwire codec to handle the possibility of error happened parallel processing for parallel vary from 1 to 16b which can The Error correction codec for multi-channel solid state disk need the capability to do I/O. In this paper, we implemented the BCH codec with the error correction capability t be configurable by software. A modified version of the Euclidean Algorithms that is specifically adapted to the RS decoding error location.
作者 陈宏铭 程玉华
机构地区 北京大学上海微电子研究院
出处 《中国集成电路》 2011年第8期30-38,29,共10页 China lntegrated Circuit
关键词 MLC NAND BCH MLC NAND BCH
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献13

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同被引文献14

  • 1韩茜,罗丰,吴顺君.高速大容量固态存储系统的设计[J].雷达科学与技术,2005,3(2):110-114. 被引量：28
  • 2刘继斌,胡修林,张蕴玉.高速数据通道中的缓存研究[J].微电子学与计算机,2006,23(6):13-15. 被引量：5
  • 3江建国.BCH编译码器的设计及验证[D].上海:上海交通大学.2010.
  • 4王新梅 肖国镇.纠错码--原理与方法[M].西安：西安电子科技大学出版社,2001..
  • 5赵晓群.现代编码理论[M].武汉:华中科技大学出版社.2007:165.
  • 6Li Shu, Zhang Tong. Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding[J]. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, 2010, 18 (10) : 1412-1420.
  • 7Tanakamaru S, Hung C, Takeuchi K. Highly relia- ble and low power SSD using asymmetric coding and stripe bitline-pattern elimination programming . IEEE Journal of Solid-State Circuits, 2012, 47(1): 85-96.
  • 8Liu Wei, Rho J, Sung Wongyong. Low-power high- throughput BCH error correction VLSI design for multi-level cell NAND flash memories[C] //IEEE Workshop on Signal Processing Systems Design and Implementation. Banff: IEEE, 2006: 303-308.
  • 9Wihelm W, Kaufmann A, Noll T G. A new scalable VLSI architecture for Reed-Solomon decoders[C]// Proceedings of the IEEE 1998 Custom Integrated Cir- cuits Conference. Santa Clara: IEEE, 1998:13-16.
  • 10Sarwate D V, Shanbhag N R. High-speed architec tures for Reed-Solomon decoders[J]. IEEE Transac tion on Very Large Scale Integration(VLSI) Sys terns, 2001, 9(5): 641-655.

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中国集成电路
2011年 第8期

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