LTE基站中PDSCH高效并行计算的FPGA实现

FPGA Implementation of High Efficiency Parallel Computing of PDSCH in LTE Systems

提出一种第三代合作伙伴(3GPP)长期演进(LTE)基站中下行共享信道(PDSCH)中比特级信号处理并行计算方案,其并行运算是基于现场可编程门阵列(FPGA)的。由于下行控制信道中数据流量相对下行共享信道偏少,为了保证控制信道与共享信道下行数据的时序对齐,并且最大程度上节省硬件资源,以满足LTE系统测试要求,必须采用并行计算的处理方式。采用VHDL语言在Xilinx公司的Virtex-6系列FPGA芯片内成功对该方案进行了验证,并对其进行优化。

A parallel computing method of bit-level signal processing of the PDSCH based on FPGA in 3GPP LTE eNodeB is presented. Because of less data traffic in PDCCH compared to PDSCH, the parallel computing is used in order to make sure the data timing of PDCCH and PDSCH are aligned and hardware resources are saved greatly to meet the requirement of LTE system test. The method is successfully proved and optimized on Virtex - 6 FPGA of Xilinx by VHDL.