期刊文献+

基于信息论的时序电路演化设计

Design of Time Series Circuit Evolution Based on Information Theory
下载PDF
导出
摘要 时序电路由于存在反馈连接,因此是数字型演化硬件研究中的难点问题。为此,对时序电路的演化设计方法进行改进,提出一种针对时序电路演化的虚拟可重构平台,阐述在此平台上演化时序电路的方法。基于信息论改进电路的适应度评估方法,以目标函数和电路实测输出之间的信息熵设计适应度评估函数。实验结果表明,该方法具有较好的稳定性和全局寻优能力。 The design of circuit evolution is one of the main research directions in Evolvable Hardware(EHW).And since there are feedback connects,the time series circuit evolution has always been the key problem in the research of digital circuits’ evolution.In this paper,the design method of time series circuit evolution is improved.The virtual reconfigurable platform is put forward for the evolution of time series circuit,and it discusses the method of sequential circuits’ evolution in the platform.Based on information theory designed fitness evaluation function,it improves the convergence of the algorithm.Experimental results show that this method has better stability and global optimization ability.
出处 《计算机工程》 CAS CSCD 2012年第10期288-290,共3页 Computer Engineering
基金 国家部委基金资助项目
关键词 时序电路 虚拟可重构 信息论 演化硬件 适应度函数 有限状态机 time series circuit virtual reconfiguration information theory Evolvable Hardware(EHW) fitness function Finite State Machine (FSM)
  • 相关文献

参考文献5

二级参考文献18

  • 1原亮,丁国良,吴文术,娄建安,赵强.以FPGA和QUARTUS为基础平台的EHW环境实现[J].计算机与数字工程,2006,34(5):1-3. 被引量:6
  • 2Chu Jie, Zhao Qiang, Ding Guoliang, et al. The Implementation of Evolvable Hardware Closed Loop[C]//Proc. of 2008 International Conference on Intelligent Computation Technology and Automation. Hollywood, USA: Odyssey Press Inc., 2008: 48-51.
  • 3楮杰.基于仿生概念的容错电路自律机制研究与模型建立[D].石家庄:军械工程学院,2009.
  • 4Gads H. Evolvable Hardware: The Genetic Programming of Drawing Machines[C]//Proceedings of International Conference on Artificial Neural Nets and Genetic Algorithms. 1993: 441-449.
  • 5Yao X, Higuchi T. Promises and challenges of Evolvable Hardware[J].IEEE Transactions on Systems, Man, and Cybernetics, Part C:Applications and Reviews (S1094-6977), 1999, 29(1): 87-97.
  • 6Pauline C. Haddow, Piet van Remortel. From Here to There :Futre Robust EHW Technologies for Large Digital Designs[C]// The Third NASA/DoD Workshop on Evolvable Hardware, 2001: 232-239.
  • 7Ubar R. Test synthesis with alternative graphs[J]. IEEE Design & Test of Computers(S0740-7475), 1996, 13(1): 48-57.
  • 8Jutman A, Raik J, Ubar R. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model[C]// The 23rd International Conference on Microelectronics. 2002, 2: 621-624.
  • 9逻辑仿真[EB/OL].http://info.jlu.edu.cn/-jiaowuchu/dzjc/wang2/mulu.htm.
  • 10Garis H D. Evolvable Hardware: Genetic Programming of a Darwin Machine[C].Proc. of Artificial Neural Nets and Genetic Algorithms. Innsbruck, Austria: Springer-Verlag, 1993: 441-449.

共引文献16

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部