基于CMOS工艺的RFID双频低噪声放大器设计与仿真

Design and Simulation of RFID Dual-band LNA Based on CMOS Process

设计出一种可应用于RFID系统,同时工作在915 MHz和2.45 GHz的双频段低噪声放大器.该设计以最大程度降低噪声为目标,采用并联LC网络替代传统单一高感值电感,并引入电流复用技术,最终实现高增益低功耗的双频段低噪声放大器的设计目标.仿真结果如下:在915MHz和2.45GHz的频率下,噪声系数均小于0.6dB;S(1,1)小于—15dB;S(2,2)小于—11dB;输入驻波比≤1.4;输出驻波比≤1.8;1dB压缩点约为—16.5dBm.仿真结果表明,在两个频段中的测试结果均优于预期指标的要求,为实际双频段低噪声放大器的设计及优化提供参考。

A dual band low-noise amplifier can be used to design a RFID system while operating at 915 MHz and 2.45 GHz has been designed. The design to minimize the noise as the target, using parallel LC network instead of traditional single high inductance inductor, and then, introduction of the current reuse technology. Ultimately, achieve a high gain; low-power dual-band low-noise amplifier. The simulation results are as follows： In 915 MHz and 2.45 GHz frequencies, the noise coefficients were less than 0.6 dB; S（1,1） less than-- 15 dB; S（2,2） less than-- 11 dB; input VSWR≤ 1.4; output VSWR≤1.8; 1 dB compression point is about -- 16.5 dBrn. The simulation and comparison shows that the design in two bands in the test results were better than expected target, and provide a reference for the actual dual-band low noise amplifier reference design and optimization.