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应用于DSRC系统的5.8GHz CMOS LNA设计 被引量:3

A design of 5.8 GHz CMOS LNA for DSRC application
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摘要 基于TSMC 0.18μm CMOS RF工艺,完成了一个全集成共源-共栅低噪声放大器设计。版图后仿真结果表明:1.8V电源电压下,电路静态功耗约为17mW;在DSRC系统工作频段上,电路实现了良好的综合性能指标,输入反射系数(S11)和输出反射系数(S22)小于-15dB,增益(S21)大于14.0dB,反向隔离度(S12)达到32dB,噪声系数小于2dB,并且工作稳定。 Based on TSMC 0.18pm RF CMOS technology, a fully integrated cascade ENA is designed. In DSRC band, the circuit has perfect performance. The post-layout simulation results show that the input return loss (S11) and output return loss (S22) are lower than -15dB, the gain (S21) is greater than 14dB, the reverse isolation (|S12|) reaches 32dB and the NF is lower than 2dB. It dissipates about 17 mW at 1.SV supply voltage, and works with good stability.
出处 《电路与系统学报》 CSCD 北大核心 2012年第3期134-138,共5页 Journal of Circuits and Systems
基金 江苏省高校自然科学研究重大项目(09KJA510001) 江苏省"青蓝工程"项目资助(2010年度)
关键词 低噪声放大器 噪声系数 交通专用短程通信:不停车收费 low noise amplifier noise figure DSRC ETC
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参考文献10

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二级参考文献26

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共引文献15

同被引文献36

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