基于FPGA的键盘输入累计存储IP核的设计与验证

The Implementation and Verification of Keyboard Input and Accumulation Storage of IP Core Based on FPGA

基于FPGA设计了一款通用键盘IP核,该核主要实现对键盘输入信号的计算与存储功能,并在quartusⅡ环境下使用VHDL语言,采用自顶向下设计方式,编辑生成RTL原理图,并做了相关的时序仿真验证。经验证此IP核具有较强的鲁棒性和较高的反应速度,可作为基础输入模块,为其他模块提供有力控制输入与数据支持。

A universal keyboard IP core has been devised based on FPGA which mainly deals with the realization of calculation and storage of the keyboard-input signal. Meanwhile the new device employs VHDL language in the environment of Quartus n. Adopts top-down design method, edits and generates P, TL schematic diagram and at the same time produces related sequential simulation validation. The experiment shows the IP core has strong robustness and high response speed, can be used as the primary input module which can provide the other modules with powerful control input and data support.