5Gb/s0.18μm CMOS半速率时钟与数据恢复电路设计

Design of a 5 Gb/s Half-Rate Clock and Data Recovery Circuit in 0.18 μm CMOS Process

基于具体的系统需求,采用标准0.18μm CMOS工艺,设计了一种半速率bang-bang型时钟与数据恢复(CDR)电路。该CDR电路主要由改进型半速率鉴相器、带粗控端的环形压控振荡器(VCO)以及信道选择器等模块构成。其中,改进型半速率鉴相器通过增加四个锁存器,不但能获得较好的鉴相性能,还能使分接输出的两路数据自动实现相位对齐。带粗控端的环形VCO能够解决高振荡频率范围需求与低调谐增益需求之间的矛盾。信道选择器则能解决信道交叉出错问题。仿真结果表明,电路工作正常,在1.8V电压下,电路功耗为140mW,恢复出的时钟和数据抖动峰峰值分别为3.7ps和5ps。

Based on specific system requirements, a half-rate hang-bang clock and data recovery （CDR） was designed in 0. 18 μm CMOS process. The CDR circuit mainly consists of a revised half-rate phase detector （PD）, a ring voltage- controlled oscillator （VCO） with a coarse tuning terminal, and channel switch （CS）. With four extra latches, the revised PD not only achieved better performance, but also enabled the two-way demultiplexed output data to be aligned with each other. The ring VCA） with a coarse tuning terminal could deal with the requirement conflict between high oscillating frequency range and low turfing gain. The channel switch could deal with mistakes related to wrong channel choice. Simula- tion results showed that the circuit operated properly at 1.8 V supply voltage with 140 mW power consumption, and the peak-to-peak jitters of the recovered clock and data were 3. 7 ps and 5 ps, respectively.