一种高效雷达信号模拟器

Simulator of advanced radar echo signal

为了给某些雷达信号处理算法的研究提供一种有效验证手段,设计此款雷达信号模拟器。系统基于DSP+FPGA+DDS架构:以DSP为核心,将AD9957作为基本目标信号产生器,在DSP的控制下FPGA产生基带数据提供给上变频芯片AD9957,完成中频模拟信号的产生。该模拟器创新地利用基于乘法器的迭代算法模拟多种类型雷达回波信号,特别适合产生大时宽信号。这种架构在产生多目标,和差信号方面比传统方法更节省硬件资源。结果表明,该系统集成度高,可扩展性强,数据产生方法高效。

A new radar signal simulator was designed to provide an effective validation method for some radar signal process algorithms. A new DSP ＋ FGPA ＋ DDS architecture is introduced, in which DSP acts as central processor and AD9957 as basic target signal generator. The FPGA provides the base band data for up-frequency-convertion chip AD9957 un- der the control of DSP to generate middle-frequency analog signals. A multiplier based iterative algorithm is employed innova- tionally to simulate multiple radar echo signals. The simulator is good at wide-time-domain simulation. The new architecture can save more hardware resources in generating multiple targets and difference signals than traditional methods. The system has the features of high integration, flexible expansion and effective data generation.