摘要
通过设计实例,详细说明如何在实际设计中,应用VHDL语言和原理图设计方法来设计复杂的逻辑电路.根据VHDL的语法规则,对系统的逻辑行为进行描述,然后通过综合工具进行电路结构的综合、编译、优化,利用波形仿真工具,可在短时间内设计出高效、稳定、符合设计要求的电路,具有传统逻辑设计方法所无法比拟的优越性.
With the design example, how to apply VHDL language and principle diagram to design complex logic circuit in the actual design is detailedly explained. According to VHDL grammar rules, the system logic behavior is described, and then the inte- grated circuit structure is synthesized, compiled and optimized by comprehensive tools. Through using waveform simulation tools, the efficient, stable, comply with the requirements of the circuit can be designed in a short time and this is traditional logical design method incomparable advantages.
出处
《渭南师范学院学报》
2012年第6期24-28,共5页
Journal of Weinan Normal University
基金
陕西省军民融合研究基金项目(11JMR07)
渭南师范学院科研计划项目(10YKF012)