期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

A fast combination calibration of foreground and background for pipelined ADCs 被引量：1

A fast combination calibration of foreground and background for pipelined ADCs
原文传递
导出
摘要 This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions. This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.
作者 孙可旭 何乐年
机构地区 Institute of VLSI Design
出处 《Journal of Semiconductors》 EI CAS CSCD 2012年第6期84-94,共11页 半导体学报（英文版）
基金 supported by the National Key Project,China(No.2008zx010200001)
关键词 background calibration capacitor mismatch and gain calibration digital calibration foreground calibration pipelined analog-to-digital converter signal-shifted correlation background calibration capacitor mismatch and gain calibration digital calibration foreground calibration pipelined analog-to-digital converter signal-shifted correlation
分类号 TN792 [电子电信—电路与系统]
  • 相关文献

参考文献23

  • 1Iizuka K, Matsui H, Ueda M, et al. A 14-bit digitally self- cali- brated pipelined ADC with adaptive bias optimization for arbi- trary speeds up to 40 MS/s. IEEE J Solid-State Circuits, 2006, 41:883.
  • 2Shu Y S, Song B S. A 15-bit linear 20-MS/s pipelined ADC dig- itally calibrated with signal-dependent dithering. IEEE J Solid- State Circuits, 2008, 43:342.
  • 3Ming J, Lewis S H. An 8-bit 80-Msample/s pipelined analog-to- digital converter with background calibration. IEEE J Solid-State Circuits, 2001, 36(10): 1489.
  • 4Liu H C, Lee Z M, Wu J T. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J Solid-State Circuits, 2005, 40(5): 1047.
  • 5Fan J L, Wang C Y, Wu J T. A robust and fast digital background calibration technique for pipelined ADCs. IEEE Trans Circuits Syst I, Reg Papers, 2007, 54(6): 1213.
  • 6Ahmed I,Johns D A. An ll-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage. IEEE J Solid-State Circuits, 2008, 43(7): 1626.
  • 7Massolini R G, Cesura G, Castello R. A fully digital fast conver- gence algorithm for nonlinearity correction in multistage ADC. IEEE Trans Circuits Syst II, Express Briefs, 2006, 53(5): 389.
  • 8Galton I. Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Trans Circuits Syst II, Analog Digit. Signal Process, 2000, 47(3): 185.
  • 9Li J, Moon U K. Background calibration techniques for multi- stage pipelined ADCs with digital redundancy. IEEE Trans Cir- cuits Syst II, Analog Digit Signal Process, 2003, 50(9): 531.
  • 10Siragusa E, Galton I. A digitally enhanced 1.8-V 15-bit 40- MSample/s CMOS pipelined ADC. IEEE J Solid-State Circuits, 2004, 39(12): 2126.

同被引文献13

  • 1IIZUKA K, MATSUI H, UEDA M, et al. A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s [J. IEEE Journal of Solid-State Circuits, 2006, 41 ( 4 ) .- 883 - 890.
  • 2MING J, LEWIS S H. An 8-bit 80Msample/s pipelined analog-to-digital converter with background calibration [J. IEEE Journal of Solid-State Circuits, 2001, 36 (10) . 1489 - 1497.
  • 3SHU Y S, SONG B S. A 15-bit linear 20-MS/s pipe- lined ADC digitally calibrated with signal-dependent dithering [J]. IEEE Journal of Solid-State Circuits, 2008, 43(2): 342-350.
  • 4MASSOLINI R G, CESURA G, CASTELLO R. A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC [J]. IEEE Trans. Circuits Syst. II, Express Briefs, 2006, 53(5) .- 389 - 393.
  • 5SUN K, HE L. Parallel background calibration with signal-shifted correlation for pipelined ADC [C]// IEEE 13th International Symposium on Integrated Circuits. Singapore: IEEE, 2011, 11: 340-343.
  • 6MURMANN B, BOSER B. A 12-bit 75-MS/s pipelined ADC using opewloop residue amplification [J]. IEEE Journal of Solid-State Circuits, 2003, 38 ( 12 ) : 2040 - 2050.
  • 7MURMANN B. Digital calibration for low-power high- performance A/D conversion [D]. Berkeley: University of California Berkeley, 2003.
  • 8PENGB, LI H, LEESC, LINP F , et al. A virtual- ADC digital background calibration technique for multi- stage A/D conversion [J]. IEEE Trans. Circuits Syst.II, Express Briefs, 2010, 57(11). 853-857.
  • 9PENGB, HUANGGZ, LI H, et al. A48-mW, 12- bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS [C// IEEE Custom Integrated Circuits Conference (CICC). San Jose: IEEE, 2011: 1- 4.
  • 10YUANJ, FUNGSW, CHANKY, XUR. A 12-bit 20 MS/s 56. 3 mW pipelined ADC with interpolation- based nonlinear calibration rJ. IEEE Trans. Circuits Syst. I, Regular Papers, 2011, 59(3) : 555 - 565.

引证文献1

二级引证文献1

Journal of Semiconductors
2012年 第6期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部