摘要
对于设计像 MPEG2视频解码器的复杂系统 ,关键的难点是其系统结构的设计。文中设计了一种适合 VL SI实现的 MPEG2解码器的系统结构。它支持 MPEG2 (MP@ML)码流 ,并且兼容 MPEG1码流。为了设计和优化这个结构 ,采用硬件描述语言 VHDL 设计了系统级的 MPEG2视频解码器。此解码器在 Viewlogic系统中进行了模拟 ,并且对一些码流进行了测试验证。
For complex system like MPEG2 video decoder, the crucial difficulty is its system architecture design. In this paper, a system architecture of MPEG2 video decoder suitable for VLSI implementation is designed. This architecture is specified in MPEG2 main profile at the main level (MP@ML) and is compatible with MPEG1 bitstream. In order to design and optimize this architecture, a system level MPEG2 decoder is developed, which is described by VHDL and simulated in viewlogic environment. Some bitstreams have been tested to show its correctness.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2000年第1期60-65,共6页
Research & Progress of SSE