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An Algorithm to Obtain Circuits with Synchronous RAMs

An Algorithm to Obtain Circuits with Synchronous RAMs
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出处 《通讯和计算机(中英文版)》 2012年第5期547-559,共13页 Journal of Communication and Computer
关键词 随机存取存储器 时序电路 同步 算法 现场可编程门阵列 FPGA 用户设计 RAMS FPGA, Block RAMs, asynchronous read operations, rewriting algorithm.
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参考文献5

  • 1J. Bordim, Y. Ito, K. Nakano, Accelerating the CKY parsing using FPGAs, IEICE Transactions on Information and Systems (2003) 803-810.
  • 2J. Bordim, Y. Ito, K. Nakano, Instant specific solutions to accelerate the CKY parsing for large context-free grammars, International Journal on Foundations of Computer Science, pages, 2004, pp. 403-416.
  • 3K. Nakano, Y. Yamagishi, Hardware n choose k counters with applications to the partial exhaustive search, IEICE Transaction on Information and Systems, 2005.
  • 4Y. Ito, K. Nakano, A hardware-software cooperative approach for the exhaustive verification of the collatz conjecture, in: Proc. of International Symposium on Parallel and Distributed Processing with Applications, 2009, pp. 63-70.
  • 5M.N.I. Mondal, K. Nakano, Y. Ito, A rewriting algorithm to generate AROM-free fully synchronous circuits, in: Proc. of the First International Conference on Networking and Computing (ICNC), 2010, pp. 148-155, November.

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