NRS FPU中浮点乘、除运算的合并设计

THE UNIFIED DESIGN OF FLOATING POINT MULTIPLICATION AND DIVISION IN NRS FPU

ＮＲＳ ＦＰＵ是西北工业大学航空微电子中心研制的具有自主版权的协处理器．文中面向嵌入式应用描述了 ＮＲＳ ＦＰＵ通用路径下浮点乘、除的合并设计．主要讨论了迭代计数器、除索引寄存器与乘数寄存器的合用、ＢＯＯＴＨ译码逻辑与除法的查找表结合、以及数据缩放与移位部件的共用．并结合具体实现，对浮点除算法中实现较复杂的商位产生算法进行了改进．与其它几种常见的处理器比较显示，ＮＲＳ ＦＰＵ规模小、速度高，是嵌入式应用的最佳选择．

NRS FPU is a coprocessor that is designed and licensed by the Aviational Microelectronic Center. The unified design of floating point multiplication and division sharing general data path with other operations in NRS FPU is presented in this paper. This paper concentrates on the register acting as the division's index as well as the storage of the multiplier and iteration counter, the table combining BOOTH decoding logic with SRT lookup table, the scaler and the shifter shared by both multiplication and division operation. Finally, most complicated conversion-on-the-fly algorithm is simplified for its implementation. In comparison with other popular microprocessors, NRS FPU is the best choice for the embedded application due to its low area and high speed.