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对称薄膜双栅MOSFET温度特性的研究 被引量：1

Temperature characteristics of symmetric thin-film double-gate MOSFET
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摘要 文章对薄膜双栅MOSFET器件的温度特性进行了研究。首先对其进行理论分析,得到亚阈值电流、阈值电压和饱和电流等随温度的变化关系,并计算出理论结果,再用Medici模拟仿真加以验证,比较了不同温度下的输出特性、饱和漏电流、阈值电压与温度变化的关系,验证结果表明两者是一致的。 The temperature characteristics of thin-film double-gate MOSFET are studied in this paper. Firstly, the change of the subthreshold current, threshold voltage and saturation current with the temperature is calculated theoretically. Then by using Medici model, the separate differences of out- put specification, saturation drain current and threshold voltage under different temperatures are ana- lyzed. It is shown that the theoretical results are in accordance with the simulation ones.
作者 谌婧娇 陈军宁 高珊
机构地区 安徽大学电子信息工程学院
出处 《合肥工业大学学报（自然科学版）》 CAS CSCD 北大核心 2012年第6期776-779,共4页 Journal of Hefei University of Technology：Natural Science
基金 国家自然科学基金资助项目(60876062)
关键词 薄膜双栅MOSFET 温度 阈值电压 亚阈值电流 thin-film double-gate MOSFET temperature threshold voltage subthreshold current
分类号 TN301 [电子电信—物理电子学]
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参考文献12

  • 1Draper B L,Palmer D W. Extension of high temperature electronics[J]. IEEE Trans Components Hybrids Manufacturing Technology,1979,CHMT-2(4) : 399-404.
  • 2Shoucair F S. High-temperature latch-up characteristics in VLSI CMOS circuits. IEEE Trans Electron Devices[J]. 1988,ED-35 (12):2424-2426.
  • 3冯耀兰,翟书兵.宽温区（27～300℃）MOS器件高温特性的模拟[J].电子器件,1995,18(4):234-238. 被引量：8
  • 4Venkatesan S, Neudeek G W, Pierret R F. Dual-gate operation and volume inversion in n-channel SOl MOSFET's [J]. IEEE Elec Dev Lett,1992,13 (1):44-46.
  • 5Hisamoto D, Kaga T, Takeda E. Impact of the vertical SOI "DELTA" structure on planar device technology [J]. IEEE Trans Elee Dev, 1991,38 (6) : 1419-1424.
  • 6Ahmed S, Alam M K, Rabbi M G, et al. Quantum mechanical study of gate leakage current in double gate MOS structuresr[C]//ISDRS 2007, December 12-14, 2007, College Park, MD, USA, 2007 : 1-2.
  • 7Ge L X, Fossum J G. Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs[J]. IEEE Trans Elec Dev,2002,49 (2): 287-293.
  • 8方圆,张悦,李伟华.薄膜双栅MOSFET体反型现象的研究[J].微电子学,2005,35(3):270-274. 被引量：1
  • 9Lopez-Villanueva J A, Cartujo-Cassinello P, Gamiz F, et al. Effects of the inversion-layer centroid on the performance of double-gate MOSFETs[J]. IEEE Trans Elec Dev, 2000, 47 (1):141-146.
  • 10Arnold E, Letavic T, Merchant S, et al. High-temperature performance SOI and bulk-silicon RESURF LDMOS transistors[C]//Proceedings of 8th International Symposium on Power Semiconductor Device and ICs, ISPSD' 96, Maui HI, 1996 : 93-96.

二级参考文献20

  • 1柯导明,童勤义,冯耀兰.pn结泄漏电流对高温集成MOSFET交流性能的影响[J].固体电子学研究与进展,1993,13(2):153-160. 被引量：4
  • 2冯耀兰,翟书兵,张晓波,柯导明.MOS器件的最高工作温度及潜力开拓[J].电子器件,1994,17(4):23-29. 被引量：9
  • 3陈占平,魏丽琼,许铭真,谭长华,王阳元.通用薄膜双栅SOI　MOSFET电流模型[J].Journal of Semiconductors,1996,17(10):729-734. 被引量：7
  • 4[1]Balestra F, Cristoloveanu S, Benachir M, et al. Dou ble-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance [J]. IEEE Elec Dev Lett, 1987; 8(9): 410-412.
  • 5[2]Colinge J P(著),武国英(译).SOI技术-21世纪的硅集成电路技术[M].北京:科学出版社.
  • 6[3]Venkatesan S, Neudeck G W, Pierret R F. Dual-gate operation and volume inversion in n-channel SOIMOSFET's [J]. IEEE Elec Dev Lett, 1992; 13(1): 44-46.
  • 7[4]Hisamoto D, Kaga T, Takeda E. Impact of the verti cal SOI 'DELTA' structure on planar device technolo gy [J]. IEEE Trans Elec Dev,1991; 38 (6): 1419- 1424.
  • 8[5]Schubert M, Hofflinger B, Zingg R P. An analytical model for strongly inverted and accumulated silicon films [J]. Sol Sta Elec,1990;33 (12) :1553-1568.
  • 9[6]Ortiz-Conde A, Garcia Sanchez F J. The foundation of a charge-sheet model for the thin-film MOSFET[J]. Sol Sta Elec,1988;31(10): 1497-1500.
  • 10[7]Mazhari B, Cristoloveanu D E, loannou A L. Proper ties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's [J]. IEEE Trans Elec Dev, 1991; 38(6): 1289-1295.

共引文献7

同被引文献9

  • 1刘恩科,朱秉升,罗晋生,等.半导体物理[M].第4版.北京:国防工业出版社,2009:105.
  • 2Mahapatra S,Parikh C D,Rao V R,et al. A comprehensive study of hot-carrier induced interface and oxide trap distri- bution in MOSFET's using a novel charge pumping tech- nique[J].IEEE Transactions on Electron Devices, 2000,47 (1):171-177.
  • 3Anil K G, Mahapatra S, Eisele I. A detailed experimental in- vestigation of impact ionization in n-channel metal-oxide- semiconductor field-effect-transistors at very low drain volt- ages [J]. Solid State Electronics,2003,47(6) :995-1001.
  • 4Uorso D, Aurite S, Sciacca E, et al. Measurement of the hot earrier damage profile in LDMOS devices stressed at high drain voltage [J]. Mieroelectronics Reliability, 2007,47 (4/ 5) : 806-809.
  • 5Nigam T, Shibib A, Xu S, et al. Nature and location of inter- face traps in RF LDMOS due to hot carriers [J]. Micro- electron Eng, 2004,72 : 71- 75.
  • 6于春丽.超深亚微米LDDM0sFET器件模型及热载流子可靠性研究[D].西安:西安电子科技大学,2004.
  • 7Ashot M M, Ma T P. Lateral profiling of interface traps and oxide charge in MOSFET devices: charge pumping versusDCIV [J]. IEEE Transactions on Electron Devices, 2001, 48:2303.
  • 8Ludikhuize A W. A review of RESURF technology [C]// Proc ISPSD, 2000: 11 - 18.
  • 9易坤,张波,罗小蓉,李肇基.采用深阱结构的耐压技术[J].微电子学,2004,34(2):203-206. 被引量：2

引证文献1

合肥工业大学学报（自然科学版）
2012年 第6期

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