期刊文献+

一种新的可重复读取的同步FIFO的设计 被引量:1

A NOVE RE-READABLE SYNCHRONOUS FIFO DESIGN
下载PDF
导出
摘要 阐述了一种用于暂存数据的具有可重复读取特性的同步FIFO的设计。在一般同步FIFO结构的基础上,提出数据底部指针概念。在控制逻辑的控制下,读指针可以自动返回内部逻辑产生的数据底部,或者由外部设置为数据底部指针,实现同步FIFO中存储的数据可被重复读取的功能。文中给出相关部分的Verilog代码及仿真结果。 In this paper, a new synchronous FIFO with the re-readable feature is illustrated, which can be used to store data temporarily. Based on the general synchronous FIFO, the concept of Bottom Pointer is introduced. Under the control of logic, the read pointer may gets back automatically to the Bottom Pointer generated by the internal logic, or be set to the external Bottom Pointer. Through this special mechanism, the re-readable feature can be implemented. The related Verilog code is shown as well as the corresponding simulation results.
出处 《巢湖学院学报》 2012年第3期30-33,共4页 Journal of Chaohu University
基金 科技部中小企业技术创新基金项目(项目编号:07C26223401443)
关键词 同步FIFO 可重复读取 VERILOG synchronous FIFO re-readable Verilog
  • 相关文献

参考文献6

  • 1吴昆,黄坤,傅勇,盛翊智.一种基于格雷码的异步FIFO设计与实现[J].计算机与数字工程,2007,35(1):141-144. 被引量:6
  • 2汪东,马剑武,陈书明.基于Gray码的异步FIFO接口技术及其应用[J].计算机工程与科学,2005,27(1):58-60. 被引量:20
  • 3Clifford E. Cummings, Peter Alfke. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons. SNUG (Synopsys Users Group) San Jose, 2002 User Papers, April 2002. Available at http://www. sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf.
  • 4Clifford E. Cummings, Don Mills, Steve Golson. Asynchronous & Synchronous Reset Design Techniques - Part Deux. http:// citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.86.9871 &rep=rep l&type=pdf.
  • 5夏宇闻.Verilog数字系统设计教程[M].北京:北京航空航天大学出版社,2004..
  • 6Clifford E. Cummings. Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! http://citeseerx.ist.psu.edu/ viewdoc/download?doi=10.1.1.115.4021 &rep=repl&type=pdf.

二级参考文献9

  • 1汪东,马剑武,陈书明.基于Gray码的异步FIFO接口技术及其应用[J].计算机工程与科学,2005,27(1):58-60. 被引量:20
  • 2Smith D J. HDL Chip Design:A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog[M]. Doone Publication, 1996.
  • 3Robert M Losee. A Gray Code Based Ordering for Documents on Shelves: Classification for Browsing and Retrieval[J]. Journal of the American Society for Information Science, 1992, 43(4) : 312-322.
  • 4Scott Hauck. Asynchronous Design Methodologies: An Overview[J]. Proc of the IEEE, 1995, 83(1): 69-93.
  • 5Clifford E Cummings, Peter Alfke. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons[Z].SNUG, 2002. 1-18.
  • 6Clifford E Cummings. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs[Z]. SNUG, 2001.1-26.
  • 7William J Dally, John W Poulton. Digital Systems Engineering[M]. Cambridge University Press, 1998.
  • 8Clifford E Cummings,PeterAlfke.Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons[Z].SNUG,2002.1218.
  • 9Yusuf Duman.FIFO-construction based on a single -port SRAM:[D].Link(o)ping University library,2003

共引文献53

同被引文献14

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部