0.5μm CMOS后段平坦化工艺优化

Optimization of 0.5μm CMOS Backend Planarization

通过实验对采用SOG材料的0.5μm CMOS后段平坦化工艺进行优化。采用3因素2水平的实验设计,表明IMD1-1厚度、SOG(旋涂玻璃)厚度和etchback(反腐蚀)厚度是关键因素。将β定义为平坦化程度因子,在完全平坦化的情况下β=1;如果没有平坦化效果,则β=0。进行了两次实验发现如何提高平坦化因子。实验得到IMD1-1显著影响金属间的介质间距,它和SOG厚度强烈影响平坦化因子。最后采用DOE(实验设计)的方法优化了0.5μm CMOS的平坦化工艺,平坦化因子从70%提高到85%,平坦化均匀性同时得到改善。

This article focuses on the three variations which affected backend planarization in 0.5μm CMOS technology, and two levels three factors design of experiment method is applied. The analysis of variation results illuminate IMD 1-1 thickness, SOG thickness and etch-back thickness are important factors. The degree of planarization is defined as β .In complete planarization case, β=1. If no planarization exists, then β =0. We perform two experiments to find how can we increase the degree of planarization. The IMDI-1 affects space between metal lines, it and SOG thickness affect β strongly. We apply DOE optimized the degree of planarization of 0.5 μm CMOS technology, The β was improved from 70 percent to 85 percent, And the uniformity of planarization will be improved.