摘要
给出了宽带数字射频存储器(DRFM)雷达干扰机信号处理模块组成框图以及信号处理流程,描述了模块实现的关键技术,特别是在FPGA中实现高速信号并行处理的方法。该信号处理模块可以提供1 GHz瞬时处理带宽,存储深度达到2 048μs,可实现对新体制宽带雷达有效干扰,具有广阔的应用前景。
The composition block diagram and signal processing flowchart of the signal processor for wideband digital RF memory（DRFM） jammer are provided. The key technology of realizing the processor module is de- scribed with focus on solution to parallel high- speed signal processing in FPGA. This module can give 1 GHz processing bandwidth and 2 048 μs memory depth. It can jam new system wideband radar effectively and has wide anDlications.
出处
《电讯技术》
北大核心
2012年第6期918-921,共4页
Telecommunication Engineering
