期刊文献+

基于动态评价方法的多态电路进化设计 被引量:2

Evolutionary Design of Polymorphic Circuits Based on Dynamic Evaluation Method
下载PDF
导出
摘要 针对传统多态电路进化设计算法有效性问题,提出了基于动态评价方法的多态进化设计算法。在进化算法适应度评价阶段,利用适应度评价扩展对于不同模式下的电路分别进行评价,采用比较选择进行电路最优结构配置,防止了潜在解的丢失。将多态门与普通门混合使用,进行了Multiplier/Sorter及Majority/Parity两种多态电路的进化设计实验。实验结果表明,与传统多态电路进化算法相比所提算法进化代数减少了31.2%-77.7%,成功概率提高了11%-52%,具有进化迭代次数少、成功概率高的优势,提高了算法有效性。 To deal with the problem of the effectiveness of the traditional evolutionary design algorithm for polymorphic circuits, a new design algorithm based on dynamic evaluation method is proposed. The fitness evaluation expansion is presented to separately evaluate the circuit under different modes, while the comparison and selection is used to configure the optimal structure of the circuit in the stage of fitness evaluation, thus the loss of potential solution is avoided. The evolutionary design experiments for Multiplier/Sorter and Majority/Parity circuits are conducted by combining the polymorphic gate with conventional gate. The experimental results show that compared with the conventional algorithm, the iterations of evolution is decreased by 31.2 %-77.7% and the success probability is increased by 11 %-- 52%. The proposed algorithm has the less iterations and the higher probability of success, thus a better effectiveness.
出处 《南京航空航天大学学报》 EI CAS CSCD 北大核心 2012年第3期354-359,共6页 Journal of Nanjing University of Aeronautics & Astronautics
基金 南京理工大学自主科研专项计划(20110ZYTS028)资助项目 南京理工大学科研启动基金资助项目
关键词 多态电路 进化设计 动态评价 polymorphic circuits evolutionary design dynamic evaluation
  • 相关文献

参考文献18

  • 1Sekanina L,Starecek L,Kotasek Z. Polymorphic gates in design and test of digital circiuts[J].International Journal of Unconventional Computing,2008,(02):125-142.
  • 2Stoica A,Zebulum R S,Kyemeulen D. Polymorphic electronics[A].Heidelberg:Springer-Verlag,2001.291-302.
  • 3Ruzicka R. On bifunctional polymorphic gates controlled by a special signal[J].WSEAS Transactions on Circuits and Systems,2008,(03):96-101.
  • 4Mashayekhi M,Ardakani H H,Omidian A. A new efficient scalable bist full adder using polymorphic gates[J].Proceedings of World Academy of Science Engineering and Technology,2010.283-286.
  • 5Wang J,Chen Q S,Lee C H. Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware[J].IET Computers & Digital Techniques,2008,(05):386-400.
  • 6Lohn J D,Hornby G S. Evolvable hardware:Using evolutionary computation to design and optimize hardware systems[J].IEEE Computational Intelligence Magazine,2006,(01):19-27.doi:10.1109/MCI.2006.1597058.
  • 7Sekanina L. Evolvable hardware:from applications to implications for the theory of computation[A].Heidelberg:Springer-Verlag,2009.24-36.
  • 8Stoica A,Zebulum R S,Guo X. Taking evolutionary circuit design from experimentation to implementation:some useful techniques and a silicon demonstration[J].Computers and Digital Techniques,2004,(04):295-300.
  • 9Luo W,Zhang Z,Wang X. Designing polymorphic circuits with polymorphic gates:a general design approach[J].IET Circuits Devices &Systems,2007,(06):470-476.doi:10.1049/iet-cds:20070057.
  • 10Miller J F,Harding S L. Cartesian genetic programming[A].New York,USA:ACM,2010.2927-2948.

二级参考文献8

  • 1Miller J F, Smith S L. Redundancy and computational efficiency in cartesian genetic programming [ J ]. IEEE Trans on Evolutionary Computation,2006,10(2):167 - 174.
  • 2Yao X, Higuichi T. Promises and challenges of evolvable hardware [ J ]. IEEE Trans on Systems, Man and Cybernetics - Part C: Applications and Reviews, 2005, 14(3) :549-553.
  • 3Thompson A, Layzell P, Zebulum R S. Explorations in design space: Unconventional electronics design through artificial evolution[J]. IEEE Trans on Evolutionary Com- putation, 1999,3 (3) : 167-196.
  • 4Coello C A, Christiansen A D. Use of evolutionary techniques to automate the design of combinational circuits [ J ]. International Journal of Smart Engineering System Design,2000,2(4) :299-314.
  • 5Miller J F, Job D, Vassilev V K. Principles in the evolu- tionary design of digital circuits--Part 1 [J]. Genetic Programming and Evolvable Machines ,2000,1 ( 1 ) :8-35.
  • 6Stomeo E,Kalganova T,Lambert C. Generalisec disjunction decomposition for evolvable hardware [ J ]. IEEE. Trans on Systems,Man and Cybernetics-Part C: Applications and Reviews ,21306,36( 5 ) : 1(124-1043.
  • 7赵曙光,杨万海.基于函数级FPGA原型的硬件内部进化[J].计算机学报,2002,25(6):666-669. 被引量:36
  • 8赵曙光,刘贵喜,王军宁,杨万海.基于自适应遗传算法的模拟电路自动设计方法[J].电子学报,2004,32(4):680-683. 被引量:5

共引文献5

同被引文献23

  • 1陈晓梅.一种简化的模拟电路测试性评价方法[J].电子产品可靠性与环境试验,2007,25(5):25-29. 被引量:1
  • 2郭亚军,姚远,易平涛.一种动态综合评价方法及应用[J].系统工程理论与实践,2007,27(10):154-158. 被引量:172
  • 3Landauer R.Irreversibility and heat generation of the computing process[J].IBM Journal of Research and Development,1961,5(3):183-219.
  • 4Bennett C H.Notes on Landauer's principle,reversible computation,and Maxwell's demon[J].Studies in History and Philosophy of Science Part B:Studies in History and Philosophy of Modern Physics,2003,34(3):501-510.
  • 5冯冉.可逆逻辑电路综合方法研究[D].南京:南京航空航天大学,2011.
  • 6Rice J E.A new look at reversible memory elements[C]//IEEE International Symposium on Circuits and Systems.Piscataway,NJ:IEEE,2006:1243-1246.
  • 7Thapliyal H,Ranganathan N.Design of reversible latches optimized for quantum cost,delay and garbage outputs[C]// 23th International Conference on VLSI Design.Piscataway,NJ:IEEE,2010:235-240.
  • 8Sayem A S M,Ueda M.Optimization of reversible sequential circuits[J].Journal of Computing,2010,2(6):208-214.
  • 9Thapliyal H,Zwolinski M.Reversible logic to cryptographic hardware:A new paradigm[C]// 49th IEEE International Midwest Symposium on Circuits and Systems.Piscataway,NJ:IEEE,2006:342-346.
  • 10Nayeem N M,Hossain M A,Jamal L,et al.Efficient design of shift registers using reversible logic[C]// 2009 International Conference on Signal Processing Systems.Piscataway,NJ:IEEE,2009:474-478.

引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部