基于FPGA的可重构JH算法设计与实现

Design and Implementation of Reconfigurable JH Algorithm Based on Field Programmable Gate Array

针对现有可重构JH算法硬件实现方案吞吐量较低的问题,利用查找表方法对S盒进行优化,使改进的JH算法在现场可编程门阵列上实现时具有速度快和面积小的特点,在此基础上提出一种可重构方案。实验结果证明,该方案最高时钟频率可达322.81 MHz,占用1 405 slices,具有资源占用少、性能参数较好、功耗较低等特点。

The throughput of the existing implementation of the reconfigurable JH algorithm is relatively small,thus,this paper optimizes the S-box and proposes a new reconfigurable JH hardware implementation.Experimental results show that the proposed design achieves 322.81 MHz clock frequency using 1 405 slices,which has the advantages of less hardware resources,better performance,and lower power consumption than the existing designs.