期刊文献+

使用测试图形法优化亚分辨率辅助图形

Optimizing Sub-resolution Assist Features Using Test Pattern Method
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摘要 在亚波长光刻领域,基于规则插入亚分辨率辅助图形是一种重要的技术。现有的方法需要利用经验改善亚分辨率辅助图形,且不考虑光学邻近校正的效果。提出了一种新的利用测试图形优化亚分辨率辅助图形的方法。与一般的光学邻近校正流程结合,该方法能解决工艺窗口过小和亚分辨率辅助图形刻出等问题。通过对标准电路版图的测试,对边放置误差和工艺窗口进行了测量。边放置误差相比传统方法减小了10%,同时,不同工艺窗条件下的边放置误差也有改善。 In the field of sub-wavelength lithography, the rule-based sub-resolution assist features insertion is an important technology. Regardless of optical proximity correction effect, the conventional method needs experience to better SRAF. A new optimizing SRAF method using test patterns is presented. Combined with conventional optical proximity correction flow, it can solve problems such as small process window and SRAF print-out. Edge placement error (EPE) and process window are measured and tested on the standard benchmark circuits. The EPE has decreased 10%, while all EPEs under different process windows have also bettered.
出处 《华东理工大学学报(自然科学版)》 CAS CSCD 北大核心 2012年第3期365-369,共5页 Journal of East China University of Science and Technology
基金 国家"十一五"高端通用芯片科技重太专项(2008ZX01035-001-06)
关键词 可制造性设计 光刻 亚分辨率辅助图形 光学邻近校正 design for manufaeturability (DFM) lithography sub-resolution assist features (SRAF) optical proximity correction (OPC)
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  • 1郝跃,朱春翔,张卫东.集成电路功能成品率模拟与设计方法[J].Journal of Semiconductors,1996,17(9):677-682. 被引量:4
  • 2田之勤.纳米工艺可制造性设计EDA技术[J].中国集成电路,2007,16(2):30-38. 被引量:1
  • 3王俊平,郝跃,张俊明.Yield estimation of metallic layers in integrated circuits[J].Chinese Physics B,2007,16(6):1796-1805. 被引量:2
  • 4MOORE G E. Cramming more components onto integrated circuits [J]. IEEE Electronics Magazine, 1965. 38(8) : 114-117.
  • 5Semiconductor Industry Association International Technology Roadmap for Semiconductors 2006 [EB/OL]. http: // public itrs net/, 2006.
  • 6FULLER B. What's yield got to do with IC design? [EB/OL]. http://www, eetimes, com.
  • 7LEE F, IKEUCHI A, TSUKIBOSHI Y, et al. Critical area optimizations improve IC yields [EBIOL]. http:// www. eetimes, com/news/design/show Article. Jhtml? Article ID= 175802288, 2006.
  • 8STAPPER C H. Modeling of defects in integrated circuits photolithographic patterns [J]. IBM J Resear Develop, 1984, 8(4): 461-475.
  • 9WALKER H, DIRECTOR S W. VLASIC: a catastrophic fault yield simulator for integrated circuits [J]. IEEE Trans Comp Aid Des Integr Circ and Syst, 1986, 5(4): 541-556.
  • 10RIVERS M. Random yield simulation applied to physical circuit design [C] // MOORE W R, MALY W, STROJWAS A, Eds Yield modeling and defect tolerance in VLSI circuits. Bristol, UK:Adam Hilger Ltd, 1988.

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