一种单端10-bit SAR ADC IP核的设计

Design of a 10 bit single-ended SAR ADC IP core

本设计通过采用分割电容阵列对DAC进行优化,在减小了D/A转换开关消耗的能量、提高速度的基础上,实现了一款采样速度为1 MS/s的10-bit单端逐次逼近型模数转换器。使用cadence spectre工具进行仿真,仿真结果表明,设计的D/A转换器和比较器等电路满足10-bit A/D转换的要求,逐次逼近A/D转换器可以正常工作。

A A 10-bit-l-MS/s single-ended successive approximation register （SAR） analog-to-digital converter （ADC） that uses a split capacitor array to optimize the digital-to-analog converter （DAC） is presented, increase speed and reduce switching energy when the digital signal to analog signal converting. The simulation results which use the cadence spectre show that the proposed digital-to-analog converter, eomparator and other circuits meet the requirements of the 10-bit analog-to-digital converter, the successive approximation register analog-to-digital converter can work successfully.