摘要
一位全加器是组成二进制加法器的基本组成单元,在对现有全加器电路研究分析的基础上,提出了基于多数决定逻辑的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。
1-bit Full Adder is a elementary unit in arithmetic operation,A new low power one bit full adder cell Based on Majority Function is presented in this paper after studying and analyzing those published,which is composed of input capacitors and CMOS inverters.the full adder was simulated by PSPICE,The results shows that the new design can realize the logic function of a full adder successfully.
出处
《科技通报》
北大核心
2012年第6期155-157,160,共4页
Bulletin of Science and Technology
基金
四川省教育厅科研项目(09ZC073)