埋栅结构静电感应晶体管耐压容量与I-V特性的改善

Improvements on the Voltage Resistant Capability and I-V Characteristics of Static Induction Transistor with Buried Gate Structure

静电感应晶体管(SIT)有源区外围边界各种寄生电流的存在,不仅造成了阻断态下漏电增大,导致I-V特性异常,造成器件性能劣化,并且降低了器件的成品率。在器件有源区周围设计了保护沟槽,形成了槽台结构的孤岛,从物理上有效地切断了可能的寄生电流,改善了器件的耐压能力,优化了I-V特性。槽台结构通过对表面的台面造型来控制表面电场,能有效提高器件的击穿电压,改善器件电性能。

The various probable parasitical currents at the boundary area outside active re-gion of static induction transistor （SIT） may result in an increase of leakage current on blocking state and abnormal distorted I-V characteristics, which deteriorate electrical performances of SIT. A protecting canal surrounding the active land mesa, for cutting off the various probable proves the voltage resistant capability and I-V tecting canal is also represented in this paper. region of SIT is designed to form an isolated is-parasitical current physically. This structure im-characteristics. The technology for etching pro-tecting canal is also represented in this paper.