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面向三维集成封装的硅通孔电特性分析 被引量:3

Analysis of Electrical Characteristics of Through Silicon Via in 3D Integration
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摘要 主要针对三维集成封装中的关键技术之一的硅通孔互连技术进行电性能研究。首先简要介绍了硅通孔互连技术的背景,利用三维全波电磁仿真软件建立地-信号-地TSV模型,对其TDR阻抗和时域TDR/TDT信号进行分析,同时仿真分析了TSV互连线及介质基板所使用的材料和TSV半径、高度、绝缘层厚度等物理尺寸对三维封装中TSV信号传输性能的影响。研究结果可为工程设计提供有力的技术参考,有效地用于改善互连网络的S21,提高三维集成电路系统的性能。 The electrical characteristics of through silicon vias (TSVs) interconnect technology, which e- merged as one of the key technologies in 3 D integration package, are analyzed. Brief background of TSV technology is given. Then, a 2-tier ground-signal-ground TSV (GSG-TSV) is investigated in time domain and frequency domain using 3D full wave field solver. And the TDR impedance is shown as well as TDR/ TDT signals. At last, the impact of physical configurations and materials on TSV electrical performance is evaluated and analyzed in details. From these preliminary results, S21 in a network could be improved and the performance of 3D circuits and systems would be enhanced.
作者 贺翔 曹群生
出处 《中国电子科学研究院学报》 2012年第3期302-306,共5页 Journal of China Academy of Electronics and Information Technology
关键词 硅通孔 三维集成 TDR/TDT 时域 物理尺寸 电导率 信号传输性能 TSV 3D integration TDR/TDT time domain physical configurations conductivity elec- trical performance
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  • 1P.Ramm, M.J.Wolf, A.Klumpp, et al. Through silicon via technology:processes and reliability for wafer-level 3D system integration[C]. 2008 Electronic Components and Technology Conference, 2008: 841-846.
  • 2Peter Ramm, Armin Klumpp, Josef Weber, et al. 3D integration technologies[C]. 2009 Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS, 2009: 71-73.
  • 3Rao R. Tummala. SOP: What is it and Why? A New Microsystem-Integration Technology Paradigm-Moore' s Law for System Integration of Miniaturized Convergent System of the Next Decade [J]. IEEE Transactions on advanced packaging, 2004, 27 ( 2 ) : 241-249.
  • 4Rao R. Tummala, Madhavan Swaminathan. Introduction to System-on-Package (SOP) [M].McGraw-Hill Companies, 2008.25-60.
  • 5Gilles Poupon, System on Wafer : Proceedings of the Nicolas Sillon, David Henry, et al. A New Silicon Concept in SiP [J]. IEEE, 2009, 97 ( 1 ) : 60-69.
  • 6M.J.Wolf, P.Ramm, A.Klumpp, et al. Technologies for 3D Wafer Level Heterogeneous Integration [C].2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 2008: 123-126.
  • 7Jean-Charles Souriau, Olivier Lignier, Michel Charrier, et al. Wafer Level Processing of 3D System in Package for RF and Data Applications [C].2005 Electronics Components and Technology Conference, 2005: 356-361.
  • 8Linda Katehi, Barry Perlman, William Chappell, et al. Three Packaging architectures Dimensional Integtation and on-wafer for Heterogeneous wafer-scale circuit [R]. University of Illinois, Urbana- Champaign, IL, 2006.
  • 9X.Sun, S.Brebels, S.Stoukatch, et al. Demonstration Heterogeneous Integration of Technologies for a Ku-Band SiP Doppler Radar [C].38th European Microwave Conference, 2008:1497-1500.
  • 10Patty Chang-Chien. Wafer-Level Packaging and Wafer-Scale Assembly Technologies [EB/OL]. http: //www.gaasmantech.org/Conference% 20Information/workshops/2010/index2010WS.html, 2010-5-17.

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