摘要
基于预放大正反馈锁存比较理论,给出了一种8bit 8Gs/s高速比较器的设计.该比较器采用预放大器结构以提高分辨率、加快比较过程,采用主从锁存器降低亚稳态发生概率,采用输出缓冲器改善输出波形、提供测试接口;在HHNEC 0.18μm SiGe BiCMOS工艺下,采用Cadence Spectre进行仿真,结果显示,该比较器精度为4mV,输出摆幅±300mV,锁存时间37ps,过驱动恢复时间22ps,功耗约57mW,表现出良好的性能.
A high speed comparator is presented in this paper,which is designed based on the theories of pre-amplifier and positive feedback.This comparator consists of a preamplifier,a master-slave latch,and an output buffer,to improve the resolution and decrease the occurrence probability of metastability.The comparator is fabricated in HHNEC 0.18μm SiGe BiCMOS process and is simulated using Cadence Spectre.The simulation results show that the resolution of the comparator is 4mV,and the differential output voltage swing is±300mV.The latch time and the recovery time of the comparator are relatively 37ps and 22ps,with about 57mW power consumption.
出处
《微电子学与计算机》
CSCD
北大核心
2012年第7期51-54,共4页
Microelectronics & Computer
关键词
锗硅
高速比较器
主从锁存器
精度
SiGe
high speed comparator
master-slave latch
resolution
