摘要
本文介绍了一种小步进、低相噪、低杂散、捷变频锁相频率综合器的设计与实现,本设计选用超低相噪锁相环芯片,采用小数分频实现小步进,通过双锁相环"乒乓"工作实现捷变频,经过对环路参数的精心设计,较好的实现了相位噪声、杂散等技术指标。
Development and implementation of a small step, low phase noise, low spur, agile PLL frequency syn-thesizer are presented. Ultralow phase noise PLL chip is selected in the design, using decimal frequency divider to implement small step, and using ping-pang operation of double PLLs to realize frequency agile. The technical spec-ifications like phase noise, spurious are better achieved by carefully designing loop parameters.
出处
《火控雷达技术》
2012年第2期59-62,共4页
Fire Control Radar Technology
关键词
小步进
低相噪
低杂散
捷变频
锁相频率综合器
small step
low phase noise
low spurious
frequency agile
PLL frequency synthesizer
