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Bit-stream linear artificial neural networks based on Sigma-delta modulation 被引量：2

Bit-stream linear artificial neural networks based on Sigma-delta modulation
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作者 梁勇 Wang Zhigong Meng Qiao Guo Xiaodan
机构地区 Institute of RF-&OE-ICs
出处 《High Technology Letters》 EI CAS 2012年第2期120-123,共4页 高技术通讯（英文版）
基金 Supported by the National Natural Science Foundation of China （No. 60576028） and the National High Technology Research and Development Program of China （No. 2007AA01Z2a5）
关键词 线性神经网络 人工神经网络 比特流 Σ-Δ调制 基础 自适应噪声抵消 SIGMA-DELTA 现场可编程门阵列 bit-stream, artificial neuron, Sigma-delta, linear artificial neural networks, field programmablegate array （FPGA）
分类号 TN74 [电子电信—电路与系统] TP183 [自动化与计算机技术—控制理论与控制工程]
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参考文献10

  • 1Zhang D, Li H, Foo S Y. A simplified FPGA implementation of neural network algorithms integrated with stochastic theory for power electronics applications. In: Proceedings of the 31 st Annual Conference of the IEEE Industrial Electronics Society, Raleigh, USA, 2005. 1018-1023.
  • 2Hu H, Huang J, Xing J G, et al. Key issues of FPGA implementation of neural networks. In: Proceedings of the 2nd International Symposium on Intelligent Information Technology Application, Shanghai, China, 2008.259-263.
  • 3Himavathi S, Anitha D, Muthuramalingam A. Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization. IEEE transactions on neural networks, 2007, 18(3): 880-888.
  • 4Katao T, Hayashi K, Fujisaka H, et al. Sorter-based Sigma-delta domain arithmetic circuits. In: Proceedings of the 18th European Conference on Circuit Theory and Design, Seville, Spain, 2007. 679-682.
  • 5Pneumatikakis A, Deliyannis T. Direct processing of Sigma-delta signals. In: Proceedings of the 3rd IEEE International Conference on Electronics, Circuits, and Systems, Rodos, Greece, 1996.13-16.
  • 6Ng C W, Wong N, Ng T S. Bit-stream adders and multipliers for tri-level Sigma-delta modulators. IEEE Transactions on Circuit and System - I1: Express Briefs, 2007, 54(12): 1082-1086.
  • 7Ng C W, Wong N, Ng T S. Quaddevel bit-stream adders and multipliers with efficient FPGA implementation. Electronics Letters, 2008, 44(12): 722-724.
  • 8Hayashi K, Katao T, Fujisaka H, et al. Piecewise linear circuits operating on first-order multi-level and second-order binary Sigma-delta modulated signals. In: Proceedings of the 18th European Conference on Circuit Theory and Design, Seville, Spain, 2007.683-686.
  • 9Liang Y, Wang Z G, Meng Q, et al. Design of high speed high SNR bit-stream adder based on EA modulation. Electronics Letters, 2010, 46(11):752-753.
  • 10Fujisaka H, Kurata R, Sakamoto M, et al. Bit-stream signal processing and its application to communication systems, lEE Proceedings-Circuits, Devices, and Systems, 2002, 149(3): 159- 166.

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High Technology Letters
2012年 第2期

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