可编程数字逻辑器件中数字锁相环的实现

Implementation of Digital Phase-locked Loop in Programmable Logic Device

介绍一种超前一滞后型住同步提取数字锁相环。它是根据应用的场合和所要求达到的性能指标进行设计，并采用可编程逻辑器件来实现。该技术通过在华北油田实际应用应行稳定可靠，捕捉时间短，抗噪声能力强，达到了设计和使用的要求。

PLL (Phase-locked loop) is an important part of communication system. Its structure is complicated and should bedesigned accowhng to particular application and realishc mpirement. In this paper, a kind of digital PLL and itS implernentation in ~le logic device are inwhuced.