摘要
提出了一种基于FPGA的HDB3编译码器的设计方案,运用QuartusII 8.0对设计方法进行了仿真分析,然后在CycloneII系列EP2C35开发板进行了实验验证。该HDB3码编译码器电路简洁,运行性能稳定可靠,克服了分离元器件带来的干扰和不易调整的缺陷。
This paer introduces a design of HDB3 codecs based on FPGA, presents the simulation with Quartus II8.0. The experiment is verified on the EP2C35 developing board of cyclone II series. The HDB3 codecs is simple in the circuit, steady and reliable in the operation, solves the issues for the separated devices experting interference and is difficult to adjust.
出处
《信息技术》
2012年第6期36-38,共3页
Information Technology
基金
广西区教育厅科研项目(2010JGA121)阶段性成果
