ECO技术在SoC芯片设计中的应用

在现阶段的SoC芯片设计中,有一半以上的芯片设计由于验证问题需要重新修改,这其中包括功能、时序以及串扰等问题。芯片设计的整个流程都要进行验证工作,工程改变命令(ECO,Engineering Change Order)用于解决芯片设计后期发现的部分问题。本文重点分析了华大九天EDA工具TimingExplorer在解决时序以及串扰等问题上的部分ECO应用。

About half of the designs need to be fixed because of verification problems in current SoC design, including function problems, timing problems and crosstaik problems. The verification job is carried out throughout the design flow, and ECO （ Engineering Change Order ） is used to solve the problems founded in the late phase. This paper focuses on the part of the ECO application of Empyrean EDA tools TimingExplorer in timing and crosstalk.