VLSI集成电路版图点到点三维电阻计算

VLSI IC Layout Point to Point 3D Resistance Extraction

在超大规模集成电路(VLSI)电路设计中,两点之间的等效电阻是设计人员所要考虑的重要参数。随着深亚微米工艺的广泛应用,版图形体日趋复杂,现有版图电阻提取工具的计算方法已难满足精度要求。本文提出了对于不同种类的三维复杂形体,其电阻网络采用不同的提取方法。对于简单形体采用解析法,对于复杂形体通过三维边界元计算方法提取版图电阻。基于提取的电阻网络,通过求解电路方程计算两点之间的等效电阻。实验表明,此方法对于实际电路设计中任意两点等效电阻计算,相比较于现有工具的方法具有计算速度快,计算精度高,计算效果好等特点。

In VLSI IC design, how to get the equivalent resistance between any two points in layout is important in order to keep the correct IC circuit function and performance. With widely usage of deep submiero process technology, the layout geometries become more complex so that traditional resistance estimation method can no longer provide sufficient accuracy. This paper presents method for the point to point resistance computation for differed geometry type. It uses analytical and integration method for manhattan geometry to extract the resistance network. The equivalent resistance then can be obtained by solving the circuit equation. For the complex geometry, it uses Boundary Element Method （ BEM ） to solve the 3D Laplace equation for getting the equivalent resistance. For the real layout data, the result shows that compared with existed methods the proposed method is much faster, more accurate and better performance.