用于流水线型ADC的运算放大器设计

Design of a operational amplifier for pipelined ADC

基于0.18μm CMOS工艺设计了一个用于流水线型ADC的全差分运算放大器,提出简化的等效模型,推导得到其传输函数,分析影响直流增益和频率特性的关键因素,优化关键节点处MOS尺寸与次极点位置,以取得较高增益和较大单位增益带宽。仿真结果表明,在1.8V电源电压下,所设计的运算放大器在负载为4pF时,直流增益为123dB,单位增益带宽为860MHz,相位裕度为68°,能满足14位、50MHz以上流水线ADC的需要。

A differential operational amplifier for pipelined ADCs is designed based on 0.18 μm CMOS technology. A simplified equivalent model is presented to derive the transfer function of the amplifier, and the critical factors which affect the DC gain and frequency characteristic are analyzed. Aspect ratio of MOSFET at the key node of the circuit and the position of the non-dominant pole are optimized to achieve larger gain and unity gain bandwidth. With a 1. 8 V power supply and4 pF capacitor load, simulation results show that the DC gain is 123 dB, unity gain bandwidth is 860 MHz and the phasemargin is 68°, which can meet the requirements of a 14 bits pipeline ADC operating at 50 MHz.