延迟锁相环的Verilog-A精确建模与仿真

Precise Modeling and Simulation of Delay-Locked Loop by Verilog-A

分析了噪声以及器件失配对延迟锁相环的抖动影响,并对延迟锁相环的各模块进行了Verilog-A精确建模和性能仿真。仿真结果表明,器件失配对延迟链中间相输出的抖动影响最大,产生了约50ps的偏移;而噪声对延迟链最后一相输出的抖动影响最大,其peak-to-peak抖动值达到85ps。另外,与电路晶体管级仿真相比,通过Verilog-A建模节省了大量仿真时间,极大地提高了设计效率。

The influence of noise and cell mismatch to the jitter performance of DLL is analyzed, and precise Verilog - A models for each module of DLL is achieved. Simulation results show that the worst jitter performance of the Voltage - Controlled Delay Line, which is about 50ps, appears in the middle tap due to cell mismatch;whereas the noise effect to Voltage - Controlled Delay Line cumulates at the last tap, and its peak - to - peak jitter value reaches to 85ps. Compared with transistor - level simulation, the use of Verilog - A modeling can save a lot of time and improve design efficiency greatly.