基于硬件逻辑的网络编码编解码算法

Co-decode algorithm of network coding with hardware logic

提出了一种基于硬件逻辑实现的通用网络编码编解码算法。编码算法运用随机线性网络编码对数据分组进行编码,解码算法则运用克莱默法则进行解码。对编码器和解码器的算法和结构进行了详细的设计,并最终运用硬件描述语言在NetFPGA开发板上实现了该设计。测试结果表明,与传统的路由节点相比,使用线速的网络编码编解码器的网络能够达到最大流最小割定理所确定的流量极限,并且端到端的传输延迟稳定在一个很小的常数上。

Practical general coder and decoder of network coding （NC） with HDL （hardware description language） logic for wire-speed nodes was presented. The NC coders applied random linear network coding （RLNC） and the decoders re- covered the original packets by Cramer＇s rule. The structures and algorithms of NC coder and decoder were designed in detail and implemented in HDL with NetFPGA boards. Comparing with traditional stored-and-forward mechanism, net- work emulations showed that networks with wire-speed NC coder and decoder nodes could achieve the capacity bound of max-flow min-cut theorem, and the end-to-end delay was guaranteed on a small constant.