基于FPGA的BLVDS高速通信总线设计

Design of BLVDS High-Speed Communication Bus Based on FPGA

测试总线是测试系统中的一个重要环节,是准确传输信号的关键。详细介绍了LVDS与BLVDS技术,在此基础上论述了BLVDS总线布置设计、PCB布线设计、数据格式设计及通信背板设计,并提出了一种基于FPGA的BLVDS总线设计,采用Verilog HDL实现FPGA内部逻辑电路设计,FPGA完成BLVDS总线上数据的接收、发送,以及数据的缓存。实验结果表明,该总线通信速度快、稳定、可靠。

Test bus is an important part of the test system. It is the key to giving the accurate signal transmission. The LVDS and BLVDS technology are introduced in detail, BLVDS bus layout design, PCB layout design, data format and communication backplane design are discussed. And a kind of FPGA-based BLVDS bus design is also presented, by using Verilog HDL to achieve the internal logic circuit design. FPGA completes receiving and sending data on the BLVDS bus, and also completes the data cache. The experimental results show that the bus communication is high-speed, stable and reliable.