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VLSI电路划分问题的分散搜索算法 被引量:7

Scatter Search Algorithm for VLSI Circuit Partitioning
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摘要 电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高. Circuit partitioning is an important stage in the very large scale integration (VLSI) physical design automation, which influences further circuit design. The VLSI circuit partitioning problem is an NPhard combinatorial optimization problem. In this paper, we propose a scatter search method for the problem, which incorporates the singlevertexmove based FiducciaMatthey ses algorithm (F'M) within the scatter search framework. The FM algorithm is used for local exploitation, while the scatter search sWategy is used for global exploration. To meet the quality and diversity of initial solutions required by the scatter search method, we incorporate the greedy randomized adaptive search procedure (GRASP) with the clustering method to generate initial solutions.Ex perimental results show that the proposed scatter search algorithm is capable of partitioning large benchmark circuits,and yields re suits better than those of the wellknown multilevel partitioning package hMetis.
作者 朱文兴 程泓
出处 《电子学报》 EI CAS CSCD 北大核心 2012年第6期1207-1212,共6页 Acta Electronica Sinica
基金 国家重点基础研究发展规划(973计划)项目(No.2011CB808000) 国家自然科学基金(No.61170308 No.61070020 No.10931003) 教育部高校博士点专项科研基金(No.20093514110004)
关键词 分散搜索 GRASP FM算法 电路划分 scatter search GRASP FM algorithm circuit partitioning
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参考文献19

  • 1王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,37(2):241-247. 被引量:18
  • 2GAREY M,JOHNSON D.Computers and Intractability:a Guide to the Theory of NP-completeness[M].New York:W.H.Freeman Company,1979.209-209.
  • 3KERNIGHAN B W,LIN S.An efficient heuristic procedure for partitioning graphs .Bell System Technical Journal,1970,49:291-307.
  • 4FIDUCCIA C M,MATTHEYSES R M.A linear time heuristic for improving network partitions .Proceedings of the 19th ACM/IEEE Design Automation Conference .New York:The Institute of Electrical and Electronics Engineers Press,1982.175-181.
  • 5ALPERT C J,HUANG J H,KAHNG A B.Recent directions in netlist partitioning[J].Integration,the VLSI Journal,1995,19(1):1-81.
  • 6MORAGLIO A,KIM Y H,YOON Y,et al.Geometric crossovers for multiway graph partitioning[J].Evolutionary Computation,2007,15(4):445-474.
  • 7罗胜钦,马萧萧,陆忆.基于改进的NSGA遗传算法的SOC软硬件划分方法[J].电子学报,2009,37(11):2595-2599. 被引量:15
  • 8KARYPIS G,AGGARWAL R,KUMAR V,SHEKHAR S.Multilevel circuit partitioning[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1998,17(8):655-667.
  • 9hMetis .http://glaros.dtc.umn.edu/gkhome/metis/hmetis/download,2012.
  • 10MLPart .http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Partitioning/MLPart/,2012.

二级参考文献38

  • 1刘静,钟伟才,刘芳,焦李成.免疫进化聚类算法[J].电子学报,2001,29(z1):1868-1872. 被引量:43
  • 2Kim J S, Nicopoulos C, Vijakrishnan N, et al. A probabilistic model for soft-error rate estimation in combinational logic[A]. Proc. of the 1 st Int' l Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems, Pisa[C]. New York: Elsevier, 2034.25 - 31.
  • 3Asadi G, Tahoori M B. An analytical approach for soft error rate estimation in digital circuits[ A]. IEEE Int. Symp. on Circuits and Systems, Kobe [ C ]. Hoboken: John Wiley & Sons, 2005.2991 - 2994.
  • 4Krishnaswamy S, Viamontes G F, Markov I L, et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices[A]. Proc. of the Design, Automation and Test in Europe Conference and Exhibition, Munich[C ]. New York: ACM Society, 2005.282 - 287.
  • 5Parker K P and McCluskey E J. Probabilistic treatment of general combinational networks [J]. IEEE Trans on Computers, 1975,24(6) :668 - 670.
  • 6Parker K P and McCluskey E J. Analysis of logic circuits with faults using input signal probabilities[ J]. IEEE Trans on Computers, 1975,24(5) : 573 - 578.
  • 7Ogus R C. The probability of a correct output from a combinational circuit [ J ]. IEEE Trails on Computers, 1975,24 (5) : 534 - 544.
  • 8Zarandi H R, Miremadi S G, Ejlali A R. Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models[ A]. Proc. of the 18th IEEE Int'l Symp. on Defect and Fault-Tolerance in VLSI Systems, Boston[ C]. Washington De: IEEE Computer Society,2003.485 - 492.
  • 9Leveugle R., Cimonnet:D. ,Ammari A. System-Level Dependability Analysis with RT-Level Fault Injection Accuracy[ A]. 19th IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Cannes, France, 2004 [ C ]. Los Alamitos, California: IEEE Computer Society,2004.451 - 458.
  • 10Koren I. Signal reliability of combinational and sequential circuits[A].Proc.of the 7th Int'l Symp. on Fault-Tolerant Computing,Los Angeles[C]. Washington DC: IEEE Computer Society, 1977.162 - 167.

共引文献46

同被引文献64

  • 1刘霞,齐欢.最小-最大车辆路径问题的禁忌搜索算法[J].系统工程,2007,25(1):49-52. 被引量:12
  • 2Ungar L Y. Boundary scan as a system-level diagnostic tool [C]// AUTOTESTCON, 2012 IEEE (S1088-7725). USA: IEEE, 2012: 34-38.
  • 3Riesen K, Bnnke H. Graph classification based on vector space embedding [J]. International Journal of Pattern Recognition and Artificial Intelligence (S1793-6381), 2009, 23(06): 1053-1081.
  • 4Demoucron G, Malgrange Y, Pertuiset R. Graphes planaires: reconnaissance et construction de repr6sentations planaires topologiques [J]. Revue Franqaise de Recherche Op6rationelle (S0399-0559), 1964, 14(8): 33-47.
  • 5Myrvold W, Kocay W. Errors in graph embedding algorithms [J]. Journal of Computer and System Sciences (S0022-0000), 2011, 77(2): 430-438.
  • 6Estrella-Balderrama A, Gassner E, Jiinger M, et al. Simultaneous geometric graph embeddings [C]// Graph Drawing. Germany: Springer Berlin Heidelberg (S0302-9743), 2008: 280-290.
  • 7Geyer M, Kaufmarm M, Vrt'o I. Two trees which are self-intersecting when drawn simultaneously [J]. Discrete Mathematics (Sl052-1798), 2009, 309(7): 1909-1916.
  • 8Angelini P, Geyer M, Kaufmann M, et al. On a tree and a path with no geometric simultaneous embedding [C]// Graph Drawing. Germany: Springer Berlin Heidelberg (S0302-9743), 2011: 38-49.
  • 9Angelini P, Di Battista G; Frail F, et al. Testing the simultaneous embeddability of two graphs whose intersection is a biconnected or a connected graph [J]. Journal of Discrete Algorithms (S1570-8667), 2012, 14(7): 150-172.
  • 10Tehranipoor M, Koushanfar F.A survey of hardware trojan tax- onomy and detection[ J]. IEEE Design & Test of Computers, 2010,27(1) : 10- 25.

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