期刊文献+

基于自适应模拟退火的NoC映射算法 被引量:2

Self-adaptive simulated annealing based mapping algorithm for network on chip
下载PDF
导出
摘要 在片上网络(Network on Chip,NoC)系统中,如何完成应用特征图到结构特征图的映射是影响系统实际性能的关键步骤之一。针对NoC系统越发庞大,映射算法耗时也随之增加的问题,提出了自适应模拟退火(Self-Adaptive Simulated Annealing,SASA)的NoC映射算法。采用相对平滑方式实现温度下降过程,针对模拟退火算法易陷于局部最优的缺点,采用自适应方法改变新解生成方式,提高了算法收敛于全局最优的概率。实验结果表明,该算法与常见NoC映射算法(如基于遗传的映射算法)相比,平均性能提升了5.3%,耗时缩短了11.1%。 In the system of Network on Chip(NoC),how to map an application characterization graph to an architecture characterization graph is a key step which has a great influence on the system performance.Considering that the time consumption of mapping algorithm increases along with the increasing NoC sizes,an Self-Adaptive Simulated Annealing(SASA)based mapping algorithm for NoC is proposed.A smoothly cooling down process is adopted in the SASA.To avoid being trapped in the local optimum,the way to generate new solutions is changed adaptively in order to improve the probability of finding the global optimum.Experimental results show that compared with the traditional mapping algorithms(such as ant colony or genetic based mapping algorithms),the SASA can improve the average performance 5.3% and save the time consumption 11.1%.
作者 车晶 张瑛
出处 《计算机工程与应用》 CSCD 2012年第23期58-62,76,共6页 Computer Engineering and Applications
基金 国家自然科学基金青年科学基金(No.61106021) 江苏省高校自然研究面上项目(No.11KJB510019)
关键词 片上网络 映射算法 自适应 模拟退火 network on chip mapping algoritm self-adaptively simulated annealing
  • 相关文献

参考文献15

  • 1Bjerregaard T, Mahadevan S.A survey of research and practices of network-on-chip[J].ACM Computing Surveys, 2006,38(1 ) : 1-51.
  • 2Hu J,Marculescu R.Energy and performance-aware map- ping for regular NoC architectures[J].Computer-Aided Design of Integrated Circuits and Systems,2005,24(4): 551-562.
  • 3Marculescu R,Ogras U Y,Peh L S,et al.Outstanding re- search problems in NoC design: system, microarchitec- ture,and circuit perspectives[J].IEEE Trans on Computer- Aided Design of Integrated Circuits and Systems,2009, 28(1 ) :3-21.
  • 4王佳文,李丽,易伟,潘红兵,张宇昂,侯宁,张荣.3D NoC映射问题的动态蚁群算法[J].计算机辅助设计与图形学学报,2011,23(9):1614-1620. 被引量:10
  • 5易伟,王佳文,潘红兵,李丽.基于蚁群混沌遗传算法的片上网络映射[J].电子学报,2011,39(8):1832-1836. 被引量:12
  • 6Kikpatrick S, Gelatt C D, Vecchi M EOptimization by simulated annealing[J].Science, 1983,220 (4598) :671-680.
  • 7邓植,顾华玺,杨银堂,曾代兵.基于人工蜂群算法的低能耗高性能NoC映射[J].西安电子科技大学学报,2012,39(2):114-119. 被引量:5
  • 8葛芬,吴宁.功耗优化的片上网络协同映射[J].应用科学学报,2008,26(6):606-612. 被引量:5
  • 9Wang L, Ling X.Energy and latency aware NoC map- ping based on chaos discrete particle swarm optimiza- tion[C]//Proceedings of Communications and Mobile Computing 2010.Shenzhen: IEEE Computer Society Press, 2010 : 263 -268.
  • 10Tang Lei, Kumar S.A two-step genetic algorithm for mapping task graphs to a network on chip architecture[C]// Euromicro Symposium on Digital Systems Design (DSD' 03),2003: 180-187.

二级参考文献51

  • 1周干民,尹勇生,胡永华,高明伦.基于蚁群优化算法的NoC映射[J].计算机工程与应用,2005,41(18):7-10. 被引量:14
  • 2吴春明,陈治,姜明.蚁群算法中系统初始化及系统参数的研究[J].电子学报,2006,34(8):1530-1533. 被引量:47
  • 3JERRAYA A, TENHUNEN H, WOLF W. Multiprocessor system-on-chips [ J]. IEEE Computer Magazine, 2005,38(7): 36 -40.
  • 4BENINI L, MICHELI G D. Networks on chip: a new SoC paradigm [ J ]. IEEE Computer, 2002, 35 ( 1 ) : 70 - 78.
  • 5KIM J S, TAYLOR M B, MILLER J, WENTZLAFF D. Energy characterization of a tiled architecture processor with onchip networks [ C ]//Proceedings of the International Symposium on Low Power Electronics and Design, Seoul, 2003 : 424 - 427.
  • 6OGRAS U Y, HU Jingcao, MARCHLESCU R. Key research problems in NoC design: a holistic perspective [ C ]// Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Jersey City, 2005:69 -74.
  • 7ZHOU Wenbiao, ZHANG Yan, MAO Zhigang. Pareto based multi-objective mapping IP cores onto NoC architecture [ C ]//Proceedings of IEEE Asia Pacific Conference on Circuits and System, Singapore, 2006:331 -334.
  • 8Hu Jingcao, MARCHLESCU R. Energy-aware mapping for tile-based NoC architectures under performance constraints [ C ]//Proceedings of the Conference on Asia South Pacific Design Automation, Kitak)atshu, 2003:233 -239.
  • 9MURALI S, MICHELI G D. Bandwidth-constrained mapping of cores onto NoC architectures [ C ] / Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Paris, 2004:896-901.
  • 10TANG Lei, KUMAR S. A two-step genetic algorithm for mapping task graphs to network on chip architecture [ C ]//Proceedings of the Euromicro Symposium on Digital System Design, Belek-Antalya, 2003 : 180 - 187.

共引文献27

同被引文献4

引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部