用FPGA实现FIR数字滤波器的新方法

New Implementation Method of FIR Digital Filter by Using FPGA

在介绍用FPGA设计FIR数字滤波器常用的正则有符号数字量(CSD)编码技术和分布式算法(DA)的基础上,提出了一种改进的实现方法.该方法根据滤波器系数的特点将滤波器分为两个部分,一部分采用CSD编码技术设计,一部分采用DA算法设计.通过Quartus2软件仿真,在Cyclone EPEC6Q240C8芯片上实现了多个FIR数字滤波器.实验结果表明:改进的实现方法在一般情况下更加节约芯片面积,且实现的FIR数字滤波器完全达到了性能要求.

Based on the common implementation methods of FIR digital filter by using FPGA： canonic signed digit（CSD） coding technique and distributed arithmetic（DA）,an improved implementation method is presented.According to the feature of filter coefficients,the method divides a filter into two parts.One uses CSD coding technique to design,and the other uses DA to design.Several FIR digital filters are simulated by using Quartus2 and implemented by using Cyclone EPEC6Q240C8.The simulation and experimental result shows that the improved implementation method can generally save the area of a chip.At the same time,the filter based on this improved implementation method can thoroughly achieve the performance demand.