FPGA高层综合中的内存子系统研究综述

Review on Memory Subsystems in High Level Synthesis for FPGA

高层综合从高级编程语言对系统的行为描述出发,把系统中的计算转移到可重构的硬件中,以加速系统运行。高层综合中生成有效的内存子系统尤为重要,特别是对于数据密集型的计算。分析了现阶段FPGA高层综合技术及其内存子系统,把生成的内存子系统从体系上分为三类:DSP型体系、以CPU为核心的体系以及基于可重构内存功能单元的体系。结合实例介绍了各体系的特点,然后按照高层综合过程中的前端和后端,分类讨论了内存子系统的优化技术。经过分析评价,指出片外与片上内存间的映射、程序的有效建模等问题仍有待解决,自动化生成内存组织体系和多模块综合是可能的研究方向。

In order to accelerate the systems,High Level Synthesis（HLS） aims to map the computation of the system to the reconfigurable hardware,based on the behavioral description of the system in high level programming language.In HLS,the generation of efficient memory subsystem is critically important,especially for data-intensive computation.In this paper,the existing HLS technologies for FPGA and their memory subsystems were analyzed.The generated memory subsystems’ architectures were divided into three categories：DSP-like architecture,CPU-control architecture and architecture based on the reconfigurable memory functional units.These architectures were discussed with examples.After that,the front end and back end optimization techniques for memory subsystems in HLS were discussed respectively.In addition,the aforementioned architectures and techniques were analyzed and evaluated.Finally,the mapping between the off-chip and on-chip memories and the efficient modeling for the programs were listed as the remained problems.In HLS,syntheses for multi-module and automatic generation of the memory organization can be future research directions.