FPGA设计中的亚稳态及其缓解措施

Metastable state and mitigation measures in FPGA design

亚稳态是异步数字电路设计中的固有现象。针对FPGA产品研制中的亚稳态问题,分析了其产生的原因,阐述了亚稳态对系统可靠性的影响和评估方法,并针对单比特异步传输、多比特异步传输和复位三种情况下的亚稳态提出缓解措施。该措施可以在工程实践中参考使用。

Metastable state is inherent in asynchronous digital circuits.This paper introduces the metastable state in FPGA design and analyses the effect on system reliability. Finally,several approaches that can be used in project are discussed to mitigate the effect in the process of one bit or many bits asynchronous transmission or reset.