一种新型的级联并行过采样∑Δ调制器结构

A New Architecture of Cascaded Oversampling Sigma Delta Modulators

本文提出了一种基于时域交织技术的级联∑Δ调制器新结构 ,保留了原有时域交织结构的速度优势 ,克服了它的缺点 ,且电路简单 ,具有实用价值 .对 1- 1级联、4路并行的情况进行模拟的结果表明 :新结构比普通 2阶∑Δ调制器 ,相同时钟速率下转换精度提高 3bit,同样精度要求下转换带宽扩大一倍 ,对各路增益失配等电路非理想因素不敏感 .

Based on the time interleaved parallel technology,a new architecture of cascaded oversampling sigma delta mod ulators is presented in this paper.The new architecture overcomes the shortcoming of original time interleaved structure while retaining its high speed.With the circuit being quite simple,it can be a practically useful architecture. Simulations of the case of 1-1 cascade, 4 channel indicates that,compared with the traditional second order sigma delta modulator,the new architecture can achieve a 3bit be tter precision under the same clock rate,or double the bandwidth while keeping the same precision.Most importantly,it is insensitive to the circuit non idealities inhering to the time interleaved structure.