基于FFT-BP算法的多元域LDPC码译码器设计与FPGA实现

Design and implementation of non-binary LDPC Decoders with FPGA based on FFT-BP algorithm

GF(q)域上的LDPC码是二进制LDPC码的扩展,它具有比二进制LDPC码更好的纠错性能。FFT-BP算法是高效的LDPC码译码算法,本文在GF(4)域上探讨该算法的设计与实现。本文的创新之处在于,根据FFT-BP算法的特点设计了一种利用Tanner图进行信息索引的方式,简化了地址查询模块的设计。实验表明,在归一化信噪比为2.6dB时,译码器的误码率可达到10-6。

Low Density Parity Check （LDPC） codes over GF（q） are an extension of binary LDPC codes. Performance of LDPC codes over GF（q） is better than binary LDPC codes. FFT-BP algorithm is an efficient decoding algorithm of LDPC codes. In this paper the design of GF（4） LDPC decoders based on the FFT-BP algorithm is explored. A new method of indexing messages with the aid of Tanner graph is proposed, which leads to a simplified electronic module design for decoder address access. Experiments show that the performance of the designed decoder at a normalized signal-to-noise ratio （SNR） of 2.6dB is 10-6 in terms of the Bit Error Rate （BER）.