摘要
设计了一个用于模拟卫星电视调谐器的整数频率综合器.锁相环本振输出频率范围覆盖1.25GHz到2.8GHz,参考频率可配置为62.5kHz或31.25kHz.环路滤波器采用三阶有源滤波器,环路带宽为1kHz.电荷泵输出电流可配置为50μA或250μA.压控振荡器(VCO)采用差分反馈型结构,在偏离中心频率10kHz处的相位噪声小于-76dBc/Hz.分频器采用脉冲吞咽型结构,有15位控制位.P计数器从输入到输出只经过两个触发器和一个逻辑门,能有效减少由多级异步分频器产生的相位噪声.电荷泵充放电电流的不匹配会恶化参考杂散,这里引入了对电流过冲不匹配的考虑,在鉴频鉴相器(PFD)和电荷泵中加入了减少充放电电流过冲的措施.电路采用0.18μm RFCMOS工艺实现,面积1.3mm*1.5mm.
A frequency synthesizer has been design for analog TV tuner. The output frequency of the local oscillator covers 1.3 GHz to 2.7 GHz. The reference frequency can be set as 62.5 kHz or 31.25 kHz. The loop filter is a 3- stage active filter, and the loop bandwidth is 1 kHz. The output current of charge pump can be set as 50 μA or 250 μA. Differential feed-back structure is adopted in voltage-controlled oscillator (VCO) and the phase noise is less than--75 dBc/Hz at 10 kHz away from the central frequency. The structure of the divider is pulse-swallow and 15 control bits are used to set the divider ratio. There are two flip-flops and one logic gate when go through the P counter, which can reduce the phase noise rising from the cascade asynchronous dividers. Mismatch of current both in charging and discharging will deteriorate the reference spur performance. The paper will take the overshoot of current in charge pump into account and measures will be taken to reduce it. The chip is implemented in 0. 18 μm RFCMOS technology, the area of which is 1.3 mm * 1.5 mm.
出处
《微电子学与计算机》
CSCD
北大核心
2012年第8期144-148,共5页
Microelectronics & Computer
关键词
频率综合器
锁相环
电视调谐器
卫星电视
Frequency Synthesizer
Phase Lock Loop (PLL)
TV tuner
Satellite TV